Spartan 3E PQ208上的IP引脚的DDR和其他硬件接口？

首先，请注意，您已选择绝对最差的封装来实现同步开关问题，因为PQ208具有较长的引线框架，因此具有较高的引线电感。
话虽这么说，你需要非常小心DDR SDRAM的布局。
理想情况下，您应该将多个引脚上的引脚分散以减少接地反弹，但当然这可能会干扰可能需要另一个Vcco电压的其他逻辑连接。
另请参阅MIG是否支持您选择的器件，并使用MIG生成引脚排列以避免IOB对冲突和其他细微的布线问题。
例如，由于DDR时钟路由限制，DQS引脚无法与DQ引脚共享IOB对（这在过去让我感到烦恼，因为我的64位DIMM的可用宽度为55位）。
最后，FPGA和SDRAM之间的路由长度应该非常短，特别是因为您的4层电路板不具备最佳的传输特性。
您最好的布局可能涉及将SDRAM芯片直接放置在电路板底层的FPGA下面。
当然这意味着很多过孔。
如果你有任何备用IO引脚（不太可能，因为你已经在谈论如何使用仅输入引脚），将一些作为虚拟地点分配是有用的。
不幸的是，仅输入引脚不适用于虚拟接地。
匹配线长时，保持合理。
较短的线条比完美匹配的线条更好。
许多人使用自动路由工具将线路长度与最近的密耳相匹配，同时使所有路线更长，以便为必要的慢跑腾出空间。
在165 MHz时，您可以使用+/- 0.5“来实现跟踪匹配，而不会出现任何实际问题。还要记住除DQS和时钟之外的地址和控制线实际上是单数据速率，因此如果您需要权衡一条路由的质量
另一方面总是优先考虑DQ，DQS和其他线路上的时钟。
将大量信号连接到另一台Spartan 3E可以为您带来银行业务的灵活性。
显然，您不需要这些互连都使用相同的IO标准，因此您可以在任何银行中找到备用引脚。
除此之外：
查看实际带宽要求，看看是否可以使用较慢的SDRAM或缩小总线宽度以减少SSO问题。
考虑外包焊接和BGA封装。
在设计印刷电路板之前，无论如何都要尝试在存储器接口部分建立FPGA设计。
正如我所提到的，如果你可以使用MIG来生成SDRAM引脚，你应该相当确信不存在IO路由问题，但是建立整个设计会更好。
祝你好运，
的Gabor
-  Gabor



以下为原文

First, be aware you have chosen the absolute worst package for simultaneous switching issues, as the PQ208 has a long leadframe and therefore high lead inductance.  That being said, you need to be very careful with layout for the DDR SDRAM.  Ideally you should spread out the pins on multiple banks to reduce ground bounce, but of course that may interfere with other logic connections that may need another Vcco voltage.  Also see if MIG supports the part you chose, and generate a pinout using MIG to avoid IOB pair conflicts and other subtle routing issues.  For example a DQS pin cannot share an IOB pair with a DQ pin due to DDR clock routing constraints (This burned me in the past leaving me with a 55-bit usable width of a 64-bit DIMM).  And finally the route lengths should be very short between the FPGA and the SDRAM, especially since your 4-layer board will not have the best transmission characteristics.  Your best layout may involve placing the SDRAM chips directly under the FPGA on the bottom layer of the board.  Of course this means a lot of vias.  If you have any spare IO pins (unlikely since you're already talking about how to use the input-only pins) it would be useful to assign some as virtual grounds.  Unfortunately the input-only pins won't do for virtual grounds.
 
When matching line lengths, keep it reasonable.  Shorter lines are better than perfectly matched lines.  Many people use the automated routing tools to match line lengths to the nearest mil, while making all of the routes much longer to make room for the necessary jogs.  At 165 MHz you can get away with +/- 0.5" for trace matching without any real problems.  Also remember that address and control lines other than DQS and clock are effectively single data rate so if you need to trade off the quality of one route for another always give preference to the DQ, DQS and clock over these other lines.
 
Connecting a number of signals to another Spartan 3E can win you some flexibility with banking.  Obviously you don't need those interconnects to all use the same IO standard, so you can find spare pins in any bank for this.
 
Other than that:
 
Go through your actual bandwidth requirements and see if you can use slower SDRAMs or narrow the bus width to reduce SSO problems.
 
Consider outsourcing you soldering and going to a BGA package.
 
In any case try to build the FPGA design, at lease the memory interface portion, before you design the printed circuit board.  As I mentioned, if you can use MIG to generate the SDRAM pinout you should be fairly confident that there won't be IO routing issues, but having the entire design built would be preferable.
 
Good Luck,
Gabor 
-- Gabor

感谢Gabor的详细回复。
我对DDR SDRAM接口复杂性的初步估计还有很长的路要走，所以我暂时尝试使用Block RAM。
如果时间允许，SDRAM接口可能稍后将在修订后的设计中实施。
SDRAM本来可以用于图像缓冲，并且可以进行处理，但片上Block RAM应该能够缓冲少量数据。
给出的建议指出了一个问题，可能是因为我的所有DVI数据线都连接到一个银行。
我将不得不翻看地面反弹应用说明（xapp689）并对WASSO进行计算。
再次感谢您的提示。
-  Dex



以下为原文

Thank you Gabor with your detailed reply. My initial estimates of the DDR SDRAM interface complexity was quite a ways off so I will try to make do with Block RAM for the time being. Perhaps the SDRAM interface will be implemented later in a revised design if time permits. The SDRAM would have been used for image buffering and would have allowed for processing but the on chip Block RAM should be able to work in buffering a small amount of data coming in.
 
The advice given pointed out an issue that could have come out of interfacing all my DVI data lines to a single bank. I will have to go over the ground bounce app note (xapp689) and do the calculations with respect to WASSO.
 
Thanks again for the tips.
 
- Dex 

如果图像数据速率不是太高，您可能需要考虑使用单数据速率SDRAM作为图像缓冲区。
像Micron MT48LC4M32B2这样的单个32位宽芯片可以使用LVCMOS33 I / O以非常容易实现的125 MHz时钟速率为您提供每秒500兆字节的峰值。
我已经在许多图像处理应用中使用了这些数据流，因此您可以通过使用存储体交错来非常接近部件的理论最大数据速率。
单数据速率SDRAM的控制类似于DDR，但没有数据采样问题。
启动顺序也更简单。
另外，由于LVCMOS接口，您不需要在连接到它的存储体中使用Vref和Vrp / Vrn引脚。
我建议移动SDRAM作为低电压替代品，但既然你表示你想避免使用BGA封装，这对你来说可能不是最好的。
问候，
的Gabor
-  Gabor



以下为原文

If your image data rate is not too high you may want to consider using single data rate SDRAM as an image buffer.  A single 32-bit wide chip like the Micron MT48LC4M32B2 can give you 500 megabytes per second peak at a very easy to achieve 125 MHz clock rate using LVCMOS33 I/O.  I have used these in many image processing applications where the data is streaming, so you can run very close to the theoretical maximum data rate of the part by using bank interleaving.
 
The control for single data rate SDRAM is similar to that of DDR but without the data sampling headaches.  The startup sequence is also simpler.  Also because of the LVCMOS interface you would not need to use the Vref and Vrp/Vrn pins in the banks that connect to it.  I would suggest mobile SDRAM as a lower voltage alternative, but since you indicated you want to avoid BGA packaging this may not be the best for you.
 
Regards,
Gabor 
-- Gabor