你好Dariusz,
SPC56EL60L5CBF具有良好的信号处理引擎。
1)关于非法例外(IVOR6),是的,''指令完全由二进制0组成是非法的''
它应该是非法的,应该处理IVOR6。无论如何,我正在与专家交叉核对为什么不处理IVOR6。
2)关于HexCode,您是否检查了PowerISA V2.06B中的附录A.
最后一位efsdiv应该是2C9
就我而言,它在我的HEX代码和附录A之间匹配
(使用SPC5Studio进行测试)
3)
*)对于e200,硬件不支持浮点单元,未实现浮点单元
将尝试执行Power ISA嵌入式操作异常
FP设置时的类别浮点指令(不是IVOR7)
*)MSR [SPE]定义为SPE / EFPU可用位。
如果MSR [SPE] = 0并且通过执行efsdiv操作执行浮点除法,则不应发生异常。行为是正确的;-)
''如果MSR [SPE]被清除并执行SPE指令,则采用SPE不可用异常
尝试标量浮点指令(efsxxx)或brinc,或执行EFPU evfsxx
尝试指示。''
最好的祝福
二万
以上来自于谷歌翻译
以下为原文
Hello Dariusz ,
SPC56EL60L5CBF has well a Signal Processing Engine.
1) About Illegal Exception (IVOR6), Yes , ''An instruction is consisting entirely of binary 0s is illegal''
it should be illegal and IVOR6 should be handled. Anyway, I am cross-checking with experts why IVOR6 is not handled.
2) about HexCode , Did you check Appendix A in PowerISA V2.06B
the last bits efsdiv should be 2C9
in my case , it matches between my HEX code and the appendix A
(Test done with SPC5Studio)
3)
*)For the e200, the floating point unit is not supported in hardware, and an unimplemented
operation exception will be generated for attempted execution of Power ISA embedded
category floating point instructions when FP is set (not IVOR7)
*)MSR[SPE] is defined as the SPE/EFPU available bit.
if MSR[SPE] = 0 and division of floating-point is performed by execution of efsdiv operation, the exception should not be happened. The behavior is correct ;-)
''The SPE unavailable exception is taken if MSR[SPE] is cleared and execution of an SPE instruction other
than the scalar floating-point instructions (efsxxx) or brinc is attempted, or execution of a EFPU evfsxx
instruction is attempted.''
Best regards
Erwan