可以在FPGA内部使用CCLK时钟作为FPGA和电路板的主时钟吗？

如果我正确读取Spartan3数据表，每个Spartan3中都有一个内部硅振荡器，可以配置为CCLK时钟，用于在主串行模式下配置FPGA，并且有一个PERSIST选项可以在配置后保持时钟开启。
我的问题是，我可以在FPGA内部使用这个时钟作为FPGA和电路板的主时钟吗？
我有一个应用程序，我想在板上尽可能少的部件，我不关心主时钟频率是什么，只要它是1-50MHz时钟。要使用CCLK我必须有一个
PCB走线将CCLK输出引脚连接到另一个FPGA I / O引脚，还是可以在内部连接到它？
我没有看到有CCLK的原理图库部件。
有没有办法做到这一点？谢谢你，-J



以下为原文

If i read the Spartan3 datasheet correct, there is an internal silicon oscillator in each Spartan3 that can be configured to be the CCLK clock for configuring the FPGA in master serial mode, and there is a PERSIST option that can keep the clock on after configuration.  My question is, can I use this clock inside the FPGA as a master clock for the FPGA and the board?  I have an application where I want as few parts as possible on the board, and I don't really care what the master clock frequency is, as long as it is a 1-50MHz clock.
To use CCLK would I have to have a PCB trace connecting the CCLK output pin to another FPGA I/O pin or can I conenct to it internally?  I did not see a schematic library part that has CCLK.  Is there any way to do this?
Thank you,
-J